'無料ランチ'の終わり
数十年にわたり、開発者は「シーケンシャルな限界」と呼ばれる時代を享受してきました。この時代は デンナードスケーリング すべての新しいチップ世代でより高速なクロック速度が得られることを保証していました。しかし、私たちが直面したのは パワーウォールです。性能は周波数の関数ではなくなりました。それは 同時実行性の関数となりました。前進するためには、 計算的思考 を用いて、抽象的な 数値的手法 と現代の 並列実行モデルの間のギャップを埋める必要があります。
精度と性能のトレードオフ
ある ドメイン問題 (例:分子動力学)を マルチコアホスト から CUDAデバイス に移行することは、単なる構文の変更を超えます。それは 問題分解の変化です。並列化を行う際には、演算順序を頻繁に変更します。浮動小数点演算は結合則が成り立たないため、以下のトレードオフに直面します: 浮動小数点の精度と正確さ。並列処理の結果は数学的には正当でも、逐次処理の祖先とは数値的に異なる可能性があります。
main.py
TERMINALbash — 80x24
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QUESTION 1
What is the primary reason the 'Sequential Ceiling' was reached?
The end of Moore's Law entirely.
Thermal limits and the Power Wall hindering frequency scaling.
Lack of developer interest in C++.
The transition to quantum computing.
✅ Correct!
Dennard scaling failed because we could no longer reduce voltage as transistors got smaller, leading to unsustainable heat at high frequencies.❌ Incorrect
Transistor counts still grow, but we can't run them faster sequentially due to the 'Power Wall'.QUESTION 2
According to Amdahl's Law, if 5% of a program is strictly sequential, what is the maximum theoretical speedup?
Infinite speedup.
Approximately 20x.
5x.
100x.
✅ Correct!
1 / (0.05 + 0) = 20. The 5% sequential fraction limits the speedup regardless of parallel resources.❌ Incorrect
The sequential fraction (s) dictates the ceiling: 1/s.QUESTION 3
Why might a parallel Molecular Dynamics simulation yield slightly different results than a sequential one?
The CPU uses 64-bit while the GPU only uses 8-bit.
Floating-point addition is non-associative in parallel execution.
Parallel threads randomly skip calculations.
The CUDA compiler ignores numerical methods.
✅ Correct!
In parallel, operations are often reordered. (A+B)+C != A+(B+C) in floating-point due to rounding error accumulation.❌ Incorrect
Floating-point non-associativity is the culprit; the order of summation matters for precision.QUESTION 4
What does 'Problem Decomposition' involve in the context of parallel programming?
Breaking code into functions for readability.
Mapping domain-specific data to parallel execution models like threads or grids.
Deleting unnecessary variables to save memory.
Compiling the code for multiple OS targets.
✅ Correct!
Decomposition involves identifying how data (data-level) or functions (task-level) can be computed independently.❌ Incorrect
It refers to the structural strategy used to unlock concurrency.QUESTION 5
Which of the following describes the 'Computational Thinking' bridge?
A hardware component between the CPU and GPU.
A framework to translate domain knowledge into architecture-aware algorithms.
An automated AI tool that writes CUDA kernels.
The process of upgrading RAM on a host machine.
✅ Correct!
It is the mental framework that synthesizes domain problems with hardware constraints and programming models.❌ Incorrect
It is a strategic methodology, not a physical component.Case Study: Scaling a Fluid Dynamics Solver
Numerical Consistency in Parallel Architectures
A research team is porting a Navier-Stokes fluid solver from a single-core CPU to a cluster of CUDA devices. While the GPU version is 50x faster, the pressure values at the 100th iteration differ from the sequential version by 0.001%.
Q
1. Is this divergence likely caused by a hardware bug or a fundamental property of parallel computing?
Solution:
It is a fundamental property. In parallel reductions, the order of summation for grid cells changes. Due to floating-point non-associativity, these small rounding differences accumulate over time.
It is a fundamental property. In parallel reductions, the order of summation for grid cells changes. Due to floating-point non-associativity, these small rounding differences accumulate over time.
Q
2. How does the 'Sequential Ceiling' explain why the team chose CUDA over a faster single-core CPU?
Solution:
Dennard Scaling has ended; single-core frequency no longer increases significantly. Massive parallelism on CUDA devices is the only way to achieve the required throughput, even if it requires managing numerical accuracy trade-offs.
Dennard Scaling has ended; single-core frequency no longer increases significantly. Massive parallelism on CUDA devices is the only way to achieve the required throughput, even if it requires managing numerical accuracy trade-offs.